The Raptor-16 is a 16-bit embedded microprocessor that boasts the following features:-

Full CISC Architecture Extremely Powerful Instruction Set 12 Base Instructions with 44,961 Combinations 4 Spare Instruction slots for Signed & Unsigned Divide & Multiply Variable Length Instructions (1, 2 or 3 words) Special Quick Instructions for Extremely Compact Code 12 Addressing Modes 16 Registers 4 Condition Codes 16 Branch Conditions Directly Accessible Stack Pointer and Program Counter 5 User Ports for External Communication 1 Control Register 7 Priority Interrupts with Masks Supports any Embedded RAM up to 65535 Words Low Power Implementation Very Small Gate Count ~ 500 Flops & 900 LUT's (Xilinx) Average Processing Power ~ 8 MIP's (50MHz cystal) Performance to Size ratio of 50 Instructions per LUT Written entirely in Synthesizable VHDL (RTL)

An assembler for Raptor-16 also exists which features:-

• Source Optimization Warnings
• Compiled Source Listings
• Assembles source code transparently and then behaves just like a static RAM for simulation
• Automatic generation of initialized Xilinx Block RAM VHDL for use with Spartan 2/2E & WebPack implementation
  • 256, 512, 1024, 2048 & 4096 16-bit RAM's supported
• Automatic generation of initialized Xilinx Block RAM VHDL for use with Spartan 3 & WebPack implementation
  • 1024, 2048 4096, 8192 & 16384 16-bit RAM's supported
• Automatic generation of Xilinx RAM files (XCO & COE) for use with CoreGen* RAM implementation
  • 256, 512, 1024, 2048, 4096, 8192, 16384, 32768 & 65536 16-bit RAM's supported
• Written entirely in Behavioural VHDL

Documentation:-

• Introduction
• Instruction Set
• Instruction Density
• Execution Times
• Assembler
• User Ports
• Interrupt Mechanism
• Control Register

Validation Code:-

• asm_move_tests.txt - Checks all move addressing modes
• asm_cond_tests.txt - Checks all branch conditions
• asm_bra_tests.txt - Checks all branch addressing modes

Example Designs:-

• LCD Scroller Demo
• Pacman LCD Demo

Other Source Code:-

• asm_int.txt - Interrupt Example

* Please note CoreGen is not available in WebPack so I have no means of testing this feature.

The design source, testbench, assembler, assembly source files, instructions on how to simulate with ModelSim XE and Xilinx Place & Route scripts can all be found in the following zip:-

• raptor16.zip

The above zip also contains the necessary scripts for implementing the LCD Scroller on the Spartan-3 Retro BaseBoard from Trenz Electronic.

Although the VHDL source code (intellectual property) is targeted towards a Xilinx FPGA its low-level RTL implementation ensures an optimal result for any ASIC or FPGA architecture.