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SpaceWire Switch Core (Router)
The SpaceWire Routing Switch Core intellectual property forms an advanced (internal) multi-port packet router that conforms fully to the ECSS-E-50-12A specification. A feature list for the Switch Core is given below:-

SpaceWire Switch Core (Router)
Key Features:
  • Fully scalable design supporting 2 to 32 ports
  • Totally Symmetrical Input & Output interface
  • Supports logical & grouped addressing
  • Supports header deletion
  • Includes basic User/Configuration Port
  • Includes Input & Output FIFO's (optional)
  • Small gate count (Xilinx FPGA)
  • Low power implementation
  • Written entirely in Synthesizable VHDL (RTL)
  • Comes with an advanced testbench and example stimuli
  • IP Package contains ModelSim & Xilinx simulation & build scripts

The data input (write) and data output (read) interfaces used by the SpaceWire Switch Core are those of an Autonomous Cascadable Dual Port FIFO, which provide a perfect zero latency flow controlled handshake mechanism. The only additional signals required by the Switch Core are the active signals, which tell the switch if an external codec is in a connected or disconnected state.

Given below is a brief introduction to the SpaceWire packet format, a summary of the supported configuration commands, a bunch of example packets and the full VHDL design source. For further information please consult the freely available ECSS-E-50-12A specification and also take a look at the testbench examples stimuli.

The SpaceWire Switch Core can be used as a standalone module or connected to our SpaceWire CODEC Core to form a complete SpaceWire Routing Switch (Router).

SpaceWire Packet Format
Internal SpaceWire packets consists of a sequence of 9-bit values that make up the packet shown below.

Destination Address Cargo End of Packet

Destination Address - This field carries the location where a packet is destined and must be at least one byte long if the packet is used to traverse a switch. When a packet arrives at a switch its header byte (first byte of the Destination Address) is examined and from this the switch decides where the packet will be sent. Typically the header byte will be deleted from the Destination Address before the packet is passed on but this can be prevented. The header byte describes both the destination location and addressing mode as shown below:-

Header Byte Header Deleted Destination Mode
0 Yes Configuration Port (Internal) Packets with a configuration address are routed to the internal configuration logic.
1 to n-1 Yes Physical Port (External) Packets with a hardware address are routed to one of the physical output ports.
n to 31 Yes Invalid Packets with an invalid address are automatically discarded (swallowed) by the switch.
32 to 254 Optional Physical Port (via lookup) Packets with a logical address are routed to whatever physical port is available out of a list of physical ports. The header byte is deleted if the logical address is configured to do so.
255 Yes Reserved Packets with a reserved address are automatically discarded (swallowed) by the switch.
n represents the number of ports on a switch from 2 (1 internal plus 1 external) to 32 (1 internal plus 31 external).

Cargo - This field carries user data in the range 0 to 255 and can be anything from 0 to infinite bytes in length.

End Of Packet - This field carries a token that signals the end of a packet. There are two possible end of packet tokens as shown below:-

End of Packet Value Description
EOP (End Of Packet) 256 Packets terminated with an EOP contain a perfectly valid Destination Address and Cargo.
EEP (Error End Of Packet) 257 Packets terminated with an EEP contain a Destination Address or Cargo that is corrupt in some way.

Configuration Commands
The Configuration Port of the SpaceWire Switch Core is very bare bones sub-system and contains only what is neccessary to achieve the basic functionality of the port. The three basic commands supported by the Configuration Port are listed below:-

Serial Number - This command returns the single byte serial number of the Switch Core.

Command (to switch) :
0 0 [Return] EOP/EEP

Response (from switch) :
[Return] Serial EOP/EEP

Read Logical Address - This command returns the port mapping and header deletion flag that are set for the specified logical address.

Command (to switch) :
0 1 Logical Address (32 to 254) [Return] EOP/EEP

Response (from switch) :
[Return] Logical Address Data EOP/EEP

Write Logical Address - This command allows the port mapping and header deletion flag to be updated for a specified logical address.

Command (to switch) :
0 2 Logical Address (32 to 254) Logical Address Data EOP/EEP

This command generates no response.

All command responses from the Configuration Port are automatically routed to the port where they originated and all bad, invalid or corrupt commands are automatically discarded (swallowed).

The [Return] field is an optional field that is primarily used to route a command response across multiple switch layers.

The Logical Address Data field is a 32-bit (4 byte) field in which each bit represents a port number from 1 to 31. Bit 0 of this field is used to signal header deletion. Setting the port bits of a logical address maps a logical address to the set physical ports. One or more port bits can be set per logical address, and in the case of multiple bits, logically addressed packets will be routed to any of the free and connected physical ports specified in the list. The 32-bit layout of the Logical Address Data field is shown below:-

Port Mapping HD
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 HD
Byte 4 (first byte sent) Byte 3 Byte 2 Byte 1 (last byte sent)

The full 32-bits are always specified for the Logical Address Data even for switches having less than 32 ports. Any unused port map bits should be set to a logic '0' (no map). Setting the HD (header deletion) bit to a logic '1' will achieve header deletion for the specified logical address.

Example Packets
If we have a 17 port switch (for example) then the following packets will be handled in the following way:-

Data packet input on port 3 :
5 50 60 70 EOP
Data packet output on port 5 :
50 60 70 EOP

Data packet input on port 16 :
15 EEP
Data packet output on port 15 :

Config packet input on port 1 :
0 0 75 103 EOP
Config response output on port 1 :
75 103 Serial EOP

Config packet input on port 3 :
0 2 64 0 0 0 14 EOP
No response output for this packet!

Config packet input on port 9 :
0 1 64 EOP
Config response output on port 9 :
0 0 0 14 EOP

Data packet input on port 7 :
64 25 26 27 EOP
Data packet output on port 1, 2 or 3 :
64 25 26 27 EOP

Config packet input on port 3 :
0 2 200 0 0 5 1 EOP
No response output for this packet!

Data packet input on port 13 :
200 10 20 35 EOP
Data packet output on port 8 or 10 :
10 20 35 EOP

SpaceWire Switch Core (Router) Intellectual Property (IP) Package
The Intellectual Property package for the SpaceWire Switch Core (Router) contains all the files required to simulate the design with ModelSim.

The SpaceWire Switch Core (Router) IP is now available as shareware and can be purchased via our Contact page.

In the unlikey event that a bug is found in any of our IP it shall be fixed free of charge.