The dual port FIFO is now a standard building block in most designs, especially in the area of communications where it is used frequently for packet work. Although very useful in its basic form, the standard FIFO does lack two attributes; autonomy and cascadability. Unfortunately you cannot simply connect two FIFO's together, as shown below, and expect them to automatically transfer data.
The write side of a standard FIFO has a very subtle single-cycle handshake. When Wr_En is high the FIFO takes data if its Full flag is low. This is indeed a handshake, where data is transferred in the cycle during a high on Wr_En and a low on Full.
Unfortunately the read side of a standard FIFO does not posses the same handshake mechanism and hence cannot be directly connected to another standard FIFO. To perform a read operation two cycles are required, the first where Rd_En goes high and the second where the data is transferred.
If the need for a two-cycle read is eliminated and a pre-read circuit added, as shown below, then the standard FIFO design becomes both autonomous and cascadable.
This new FIFO design is now fully symmetrical on both its read and write interface, as can be seen by the following timing diagrams.
| Write Example |
 |
Data is transferred during the cycle when nWrite
and Full are both low, and at no other times. |
| Read Example |
 |
Data is transferred during the cycle when Empty
and nRead are both low, and at no other times.
|
Cascading the new FIFO design is now extremely easy, as is shown below. The first FIFO's Empty output is used to drive the second FIFO's nWrite input, and likewise the second FIFO's Full output is use to drive the first FIFO's nRead input. Data will be transferred when both of these connecting lines are low, i.e. when the first FIFO is not empty (has data) and the second FIFO is not full (can take data).
Details of two Autonomous Cascadable Dual Port FIFO designs are given below:-
- ac_fifo_wrap.vhd - Converts a standard dual port FIFO into an Autonomous Cascadable Dual Port FIFO. The module is simply a wrapper that adds the necessary handshake logic to a standard FIFO design.
- ac_fifo_2byte.vhd - A standalone two byte Autonomous Cascadable Dual Port FIFO that has a single cycle latency. This modules IO's are registered which makes it ideal for use alongside other modules that do not have time to register their IO's.
The design source for the above two modules can be found in the following zip:-
Although the VHDL source code (intellectual property) is targeted towards a Xilinx FPGA its low-level RTL implementation ensures an optimal result for any ASIC or FPGA architecture.
