The Raptor-16 Microprocessor execution times are made up of three elements:-
- Basic Execution Time (BET)
- Source Operand Time (SOT)
- Destination Operand Time (DOT)
Giving a total execution time of BET + SOT + DOT. See the addressing mode tables below for exact figures.
Basic Execution Time (BET) is 2 cycles with SOT and DOT given below:-
| Addressing Mode |
SOT |
DOT |
| Description |
Syntax |
| Register Direct |
Dn, An, Sp or Pc |
1 cycle |
2 cycles |
| Examples: |
LoadQ |
#0,D5 |
; Executed in 5 cycles. |
|
LoadQ |
#-128,A5 |
; Executed in 5 cycles. |
|
LoadQ |
#%001100,D1 |
; Executed in 5 cycles. |
|
LoadQ |
#$FFFF,A2 |
; Executed in 5 cycles. |
Basic Execution Time (BET) is 2 cycles with SOT and DOT given below:-
| Addressing Mode |
SOT |
DOT |
| Description |
Syntax |
| Register Direct |
Dn, An, Sp or Pc |
1 cycle |
2 cycles |
| Register Indirect |
(An), (Sp) or (Pc) |
2 cycles |
2 cycles |
| Register Indirect with Pre-Decrement |
-(An), -(Sp) or -(Pc) |
3 cycles |
2 cycles |
| Register Indirect with Post-Increment |
(An)+, (Sp)+ or (Pc)+ |
2 cycles |
2 cycles |
| Register Indirect with Displacement |
d(An), d(Sp) or d(Pc) |
4 cycles |
3 cycles |
| Immediate Quick (Address/Data) |
#n or #Label |
1 cycle |
- |
| Port Direct |
Pn |
1 cycle |
2 cycles |
| Immediate (Address/Data) |
#n or #Label |
2 cycles |
- |
| Address Direct |
n or Label |
4 cycles |
3 cycles |
| Examples: |
MoveQ |
#0,D5 |
; Executed in 5 cycles. |
|
Move |
#$F0FE,4(A5) |
; Executed in 7 cycles. |
|
Move |
$20,$40 |
; Executed in 9 cycles. |
|
Move |
A4,-(Sp) |
; Executed in 5 cycles. |
Basic Execution Time (BET) is 2 cycles with SOT and DOT given below:-
| Addressing Mode |
SOT |
DOT |
| Description |
Syntax |
| Register Direct |
Dn, An, Sp or Pc |
1 cycle |
2 cycles |
| Register Indirect |
(An), (Sp) or (Pc) |
2 cycles |
3 cycles |
| Register Indirect with Pre-Decrement |
-(An), -(Sp) or -(Pc) |
3 cycles |
4 cycles |
| Register Indirect with Post-Increment |
(An)+, (Sp)+ or (Pc)+ |
2 cycles |
3 cycles |
| Register Indirect with Displacement |
d(An), d(Sp) or d(Pc) |
4 cycles |
5 cycles |
| Immediate Quick (Address/Data) |
#n or #Label |
1 cycle |
- |
| Port Direct |
Pn |
1 cycle |
2 cycles |
| Immediate (Address/Data) |
#n or #Label |
2 cycles |
- |
| Address Direct |
n or Label |
4 cycles |
5 cycles |
| Examples: |
OrQ |
#-1,D5 |
; Executed in 5 cycles. |
|
ShlQ |
#12,10(A1) |
; Executed in 8 cycles. |
|
Add |
$400,$402 |
; Executed in 11 cycles. |
|
And |
#$FF0F,(Sp) |
; Executed in 7 cycles. |
Basic Execution Time (BET) is 2 cycles, SOT is 0 cycles and DOT is given below:-
| Addressing Mode |
No Branch
DOT |
Branch
DOT |
| Description |
Syntax |
| Register Direct |
Dn, An, Sp or Pc |
2 cycles |
5 cycles |
| Register Indirect |
(An), (Sp) or (Pc) |
2 cycles |
6 cycles |
| Register Indirect with Pre-Decrement |
-(An), -(Sp) or -(Pc) |
2 cycles |
7 cycles |
| Register Indirect with Post-Increment |
(An)+, (Sp)+ or (Pc)+ |
2 cycles |
6 cycles |
| Register Indirect with Displacement |
d(An), d(Sp) or d(Pc) |
3 cycles |
8 cycles |
| Immediate Quick (Address/Data) |
#n or #Label |
2 cycles |
5 cycles |
| Port Direct |
Pn |
2 cycles |
5 cycles |
| Immediate (Address/Data) |
#n or #Label |
3 cycles |
6 cycles |
| PC Relative Quick |
Label |
2 cycles |
5 cycles |
| PC Relative |
Label |
3 cycles |
6 cycles |
| Examples: |
Bra |
D5 |
; Executed in 7 cycles. |
|
Bra |
soc,10(A0) |
; Executed in 10 cycles if condition is met, otherwise executed in 5 cycles. |
|
BraQ |
sos,#Here |
; Executed in 7 cycles if condition is met, otherwise executed in 4 cycles. |
|
Bra |
nev,SubA |
; Executed in 5 cycles. |
Basic Execution Time (BET) is 2 cycles, SOT is 0 cycles and DOT is given below:-
| Addressing Mode |
No Branch
DOT |
Branch
DOT |
| Description |
Syntax |
| Register Direct |
Dn, An, Sp or Pc |
2 cycles |
6 cycles |
| Register Indirect |
(An), (Sp) or (Pc) |
2 cycles |
7 cycles |
| Register Indirect with Pre-Decrement |
-(An), -(Sp) or -(Pc) |
2 cycles |
8 cycles |
| Register Indirect with Post-Increment |
(An)+, (Sp)+ or (Pc)+ |
2 cycles |
7 cycles |
| Register Indirect with Displacement |
d(An), d(Sp) or d(Pc) |
3 cycles |
9 cycles |
| Immediate Quick (Address/Data) |
#n or #Label |
2 cycles |
6 cycles |
| Port Direct |
Pn |
2 cycles |
6 cycles |
| Immediate (Address/Data) |
#n or #Label |
3 cycles |
7 cycles |
| PC Relative Quick |
Label |
2 cycles |
6 cycles |
| PC Relative |
Label |
3 cycles |
7 cycles |
| Examples: |
Bsr |
P4 |
; Executed in 8 cycles. |
|
Bsr |
ugt,-(A3) |
; Executed in 10 cycles if condition is met, otherwise executed in 4 cycles. |
|
BsrQ |
sle,#Here |
; Executed in 8 cycles if condition is met, otherwise executed in 4 cycles. |
|
Bsr |
nev,#There |
; Executed in 5 cycles. |
Raptor-16 supports execution times between 4 and 11 cycles, therefor the processors power (50MHz clock) measured in MIPS (Millions of Instructions Per Second) is somewhere between 4.5 and 12.5. Based on the most likely instructions to be executed the average power should be around the 8 MIPS mark.
Since there are no busses, caches or anything else other than interrupts to get in the way of program execution then the full power of the processor is readily available and also guaranteed.
The whole philosophy behind the implementation of Raptor-16 was to achieve a small powerful processor that could execute very dense code. By no means is the state machine generated micro code optimized for speed, in fact quite the reverse, it was optimized for area at the expense of speed.
