This tutorial details the steps required for resurrecting & modifying an existing Vivado project to add interrupts to the GPIO module.

The aims of this tutorial are as follows :-

1. Setup environment
2. Copy repository
3. Resurrect project
4. Open block design
5. Re-customize ZYNQ IP
6. Re-customize AXI GPIO IP
7. Manually wire up connection
8. Run connection automation
9. Validate block design
10. Generate bitstream
11. Export Hardware Platform
12. Understand what changed
13. Archive project
14. Commit to repository

Setup Xilinx design environment for the 2020.2 toolset.

This project is not strictly a branch of the previous project but by using that as a starting point negates the need to start over. Copy the leds_switches repository and checkout the files it contains.

Resurrect the previous project in Vivado by using the regeneration Tcl script.

Once Vivado appears and completes execution of the Tcl script open the block design by clicking on Open Block Design under the IP INTEGRATOR heading inside the Flow Navigator section. Expand the Diagram by clicking on the Float icon in the Diagram pane inside the BLOCK DESIGN section.

Double click on the ZYNQ7 Processing System module to begin re-customization.

An interrupt input is required for this design to allow triggered communication from the GPIO to the ZYNQ7 Processing System To enable the IRQ_F2P connection select Interrupts, expand Fabric Interrupts, expand PL-PS Interrupt Ports, tick Fabric Interrupts and then tick Fabric Interrupts. Click OK to commit the changes.

Double click on the AXI GPIO module to begin re-customization.

Connections to both the LED's and Push Buttons on the ZedBoard are required for this design. Change the existing GPIO2 selection of sws 8bits under the Board tab to btns 5bits. Review the I/O details by selecting the IP Configuration tab. Connection to the interrupt output ip2intc_irpt on the AXI GPIO is required for this design. To enable this tick Enable Interrupt. Click OK to commit the changes.

To connect up the interrupt, left click (keeping the mouse button held down afterwards) on the ip2intc_irpt output of the AXI GPIO and drag the new connection across to the IRQ_F2P input of the ZYNQ7 Processing System, release the mouse button once the connection is established.

Although the GPIO2 connection on the AXI GPIO module has changed the block design does not reflect this yet. To make this change right click on the sws_8bits output and select Delete from the context menu. The Diagram will now display the Run Block Automation message, click on this to let Vivado automate the connections. The diagram will now reflect the changes required.

Verify the block design is error free by clicking on the Validate Design icon. Once validated save the block design and return the floating Diagram pane back to Vivado by clicking on the Dock icon.

Generate the programmable logic bitstream by clicking on Generate Bitstream under the PROGRAM AND DEBUG heading inside the Flow Navigator section.

Export the hardware platform by selecting File » Export » Export Hardware... from the main menu. Include the bitstream in the exported hardware file and save as /home/steve/projects/leds_buttons/fw/system_wrapper.xsa.

To reflect the connection change from sws_8bits to btns_5bit both the HDL Wrapper and the Constraints have been updated.

Create a project regeneration script by selecting File » Project » Write Tcl... from the main menu. Tick the Copy sources to new project & Recreate Block Designs using Tcl options and set the Output file to /home/steve/projects/leds_buttons/fw/project.tcl.

Review the script paying particular attention to any files listed below the following section of the header. There are no additional files listed for this project. Prevent the script from creating a project directory by removed this option from the create_project command.

The project.tcl is the only file that requires updating in the repository.