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Review the information the in the New Project : Create a New Vivado Project window and then click Next.
In the New Project : Project Name window set Project Name to project, Project location to /home/steve/projects/hello_world/fw & untick Create project subdirectory. Click Next to proceed.
No additional source files are required for this project so in the New Project : Project Type window tick the Do not specify sources at this time check box and then click Next.
Click on the Boards tab to view the available boards.
The Zedboard Zynq Evaluation and Development Kit isn't installed by default in this version of Vivado. To install it click on Refresh to download the latest version of the catalog, scroll down the list of available boards to find Zedboard Zynq Evaluation and Development Kit and then click on Install.
Select the ZedBoard hardware in the New Project : Default Part and then click Next.
Look over the project details in the New Project : New Project Summary window and then click Finish.
The Vivado project window now appears.
Tip: The buttons in the top menu bar of a pane provide a very useful way of expanding the working area of that pane. Maximize 
expands a pane within the project window. Float 
expands the pane beyond the project window. Restore 
reverses Maximise. Dock 
reverses Float.
The Vivado project window now changes to reflect the addition of the Diagram pane. Expand the Diagram pane outside of the Vivado window by clicking on its Float icon .
button.
Scroll down to the ZYNQ7 Processing System in the pop-up dialog and add this to the block design by double clicking on it.
The ZYNQ7 Processing System IP is now added to the block design. Let Vivado automate some of the connections by clicking on Run Block Automation.
Review the connections proposed in the Run Block Automation dialog and then click OK.
Some of the connections are now made in the block design.
The Re-customize IP window now appears.
Remove the M_AXI_GP0_ACLK connection from the ZYNQ7 Processing System as it is not required for this design and will cause an error if left unconnected. Click on PS-PL Configuration, expand AXI Non Secure Enablement, expand GP Master AXI interface and untick M AXI GP0 interface.
Remove the USB 0 connection from the ZYNQ7 Processing System as it is not required for this design. Click on MIO Configuration, expand I/O Peripherals and untick USB 0.
Remove the Timer connection from the ZYNQ7 Processing System as it is not required for this design. Click on MIO Configuration, expand Application Processor Unit and untick Timer 0.
Remove the FCLK_CLK0 connection from the ZYNQ7 Processing System as it is not required for this design. Click on Clock Configuration, expand PL Fabric Clocks and untick FCLK_CLK0.
Remove the FCLK_RESET0_N connection from the ZYNQ7 Processing System as it is not required for this design. Click on PS-PL Configuration, expand General, expand Enable Clock Resets and untick FCLK_RESET0_N.
Commit the changes made to the ZYNQ7 Processing System by clicking on OK.
in the Diagram pane or by pressing F6.
The above should result in the following dialog being presented, click OK to dismiss this. If errors are found in the block design review these and replay the relevant steps from above.
Return the floating Diagram pane back to the Vivado project window by clicking on its Dock icon .
The Generate Output Products dialog now appears. Select the required options (defaults as shown are fine) and then click Generate.
The Generate Output Products launch dialog now appears, click OK and wait for the product generation task to complete.
The Create HDL Wrapper dialog now appears. Select Let Vivado manage wrapper and auto-update and then click OK.
Float the Sources pane and fully expand the Design Sources to see the full design hierarchy which now includes the HDL wrapper. Dock the Sources pane after viewing.
The No Implementation Results Available dialog will appear on the very first run of any new project. Proceed by clicking Yes. Since synthesis and implementation have not yet been run these will be scheduled to run before the bitstream generation.
The Launch Runs dialog now appears. Select the required options (defaults as shown are fine) and then click OK.
Once the bitstream generation is complete the Bitstream Generation Completed dialog will appear. Click Cancel to dismiss this.
The generated bitstream can now be found in the impl_1 directory.
The Export Hardware Platform : Output dialog now appears. Include the generated bitstream in the exported hardware by selecting include bitstream and then clicking Next.
The Export Hardware Platform : Files dialog now appears. Export the hardware to the Vitis project directory by changing the Export to location to /home/steve/projects/hello_world/fw and then clicking Next.
The Export Hardware Platform : Exporting Hardware Platform dialog now appears. Review the information provided and then click Finish.
The exported hardware platform is a single zip file with a .xsa extension instead of a .zip. The contents of this file can be viewed by using the zip utility.
Click Yes in the Write Project to Tcl dialog to view the created Tcl file.
Review project.tcl paying particular attention to any files listed below the following section in the header. There are no additional files listed for this project.