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SpaceWire CODEC Receive FIFO Testbench
The testbench for the SpaceWire CODEC Receive FIFO is built up using the standard testbench modules,
PGive,
PTake and
PSnoop.
An illustration of how the testbench modules are connected together to form the Receive FIFO Testbench is given below:-
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| Interactive block diagram - click on area of interest to find out more. |
The FIFO has three handshake interfaces that are all controlled via stimulus files input to the
PGive and
PTake testbench modules. By adjusting the content of these files an almost infinite amount of operating scenarios can be created. In addition to the stimulus files the testbench can also change the state input, thus allowing the FIFO's operation to be validated in every SpaceWire state.
Also provided within the testbench is a self-checking mechanism that checks the following points:-
- The Receive FIFO only has 7 FCT's outstanding at any one time.
- The Receive FIFO only inputs DATA that it has given credit for.
- The Receive FIFO only outputs FCT's in the Connecting & Run states.
- The Receive FIFO only inputs DATA in the Run state.
- The Receive FIFO's input DATA is an ascending sequence with no errors.
- The Receive FIFO's output DATA is the same ascending sequence with no errors.
There are 12 sets of tests used to validate the functionality of the SpaceWire CODEC Receive FIFO, these are detailed below.
Test 1 (0us to 10us) - Error Reset state with empty FIFO
This test is used to check that during the Error Reset state the empty Receive FIFO does absolutely nothing, i.e:-
- Data is not input by the FIFO via the Input Data Interface.
- Data is not output by the FIFO via the Output Data Interface.
- FCT's are not output by the FIFO via the Output FCT Interface.
The test is set-up such that:-
- Data is provided to the FIFO at the maximum data rate.
- Data can be taken from the FIFO at the maximum data rate.
- FCT's can be taken from the FIFO at the maximum data rate.
The three handshake signals (seen in the waveform window) should remain negated throughout the test.
Test 2 (10us to 20us) - Error Wait state with empty FIFO
This test is used to check exactly the same as Test 1 but for the Error Wait state.
Test 3 (20us to 30us) - Ready state with empty FIFO
This test is used to check exactly the same as Test 1 but for the Ready state.
Test 4 (30us to 40us) - Started state with empty FIFO
This test is used to check exactly the same as Test 1 but for the Started state.
Test 5 (40us to 50us) - Connecting state with empty FIFO
This test is used to check that during the Connecting state the empty Receive FIFO does absolutely nothing other than output FCT's, i.e:-
- Data is not input by the FIFO via the Input Data Interface.
- Data is not output by the FIFO via the Output Data Interface.
- 7 FCT's are output by the FIFO via the Output FCT Interface.
The test is set-up such that:-
- Data is provided to the FIFO at the maximum data rate.
- Data can be taken from the FIFO at the maximum data rate.
- FCT's can be taken from the FIFO at the maximum data rate.
The Data In and Data Out handshake signals should remain negated throughout the test, but the FCT Out handshake signal should show 7 handshakes taking place.
Test 6 (50us to 60us) - Run state with empty FIFO
This test is used to check that during the Run state the empty Receive FIFO operates fully, i.e:-
- Data is input by the FIFO via the Input Data Interface.
- Data is output by the FIFO via the Output Data Interface.
- FCT's are output by the FIFO via the Output FCT Interface.
The test is set-up such that:-
- Data is provided to the FIFO at the maximum data rate.
- Data can be taken from the FIFO at the maximum data rate.
- FCT's can be taken from the FIFO at the maximum data rate.
The three handshake signals should show frequent handshakes taking place throughout the test. The main point to check with this test is that for every eight NChar's input to the FIFO one FCT is output from it.
Test 7 (60us to 70us) - Run state with empty FIFO becoming full
This test is used to check that during the Run state the empty Receive FIFO operates fully, i.e:-
- Data is input by the FIFO via the Input Data Interface.
- Data is output by the FIFO via the Output Data Interface.
- FCT's are output by the FIFO via the Output FCT Interface.
The test is set-up such that:-
- Data is provided to the FIFO at the maximum data rate.
- Data cannot be taken from the FIFO.
- FCT's can be taken from the FIFO at the maximum data rate.
The Data In handshake signal should show frequent handshakes all the way upto the FIFO becoming full, likewise the FCT Out handshake signal should show similar. The Data Out handshake signal should remain negated throughout the test.
The FIFO should stop inputting data when it contains 255 NChar's.
Test 8 (70us to 80us) - Run state with FIFO filling faster that it is emptying
This test is used to check that during the Run state the FIFO can handle being constantly full and nearly full, i.e:-
- Data is input by the FIFO via the Input Data Interface.
- Data is output by the FIFO via the Output Data Interface.
- FCT's are output by the FIFO via the Output FCT Interface.
The test is set-up such that:-
- Data is provided to the FIFO with a 0 to 2 cycle gap between transfers.
- Data can be taken from the FIFO but has a 2 to 4 cycle gap between transfers.
- FCT's can be taken from the FIFO at the maximum data rate.
The Data Out handshake signal should show frequent handshakes taking place throughout the test, but since the FIFO is full the Data In handshake signal should show bursts of 8 handshakes for each FCT handshake that has taken place.
Test 9 (80us to 90us) - Run state with FIFO emptying faster that it is filling
This test is used to check that during the Run state the FIFO can handle being constantly empty and nearly empty, i.e:-
- Data is input by the FIFO via the Input Data Interface.
- Data is output by the FIFO via the Output Data Interface.
- FCT's are output by the FIFO via the Output FCT Interface.
The test is set-up such that:-
- Data is provided to the FIFO with a 25 to 30 cycle gap between transfers.
- Data can be taken from the FIFO but has a 0 to 1 cycle gap between transfers.
- FCT's can be taken from the FIFO at the maximum data rate.
The three handshake signals should show frequent handshakes taking place throughout the test, but the Data Out handshake should be much more frequent than the Data In handshake until the FIFO becomes empty, after this their rates should be very similar.
Test 10 (90us to 100us) - Run state changing to Error Reset state with full FIFO
This test is used to check that during the Error Reset state the FIFO correctly adds an EEP to the received packet. Since the FIFO is first filled to 100% this test also checks that there is room for the extra EEP, i.e:-
- Data is input by the FIFO via the Input Data Interface, but then is not input during Error Reset state (but EEP is written into FIFO).
- Data is output by the FIFO via the Output Data Interface.
- FCT's are output by the FIFO via the Output FCT Interface, but then are not output during Error Reset state.
The test is set-up such that:-
- Data is provided to the FIFO at the maximum data rate.
- Data cannot be taken from the FIFO.
- FCT's can be taken from the FIFO at the maximum data rate.
The Data In handshake signal should show frequent handshakes all the way upto the FIFO becoming full, likewise the FCT Out handshake signal should show similar. The Data Out handshake signal should remain negated throughout the test. No handshakes should be seen during the Error Reset state.
The result from this test is shown in the next one.
Test 11 (100us to 110us) - Error Reset state changing to Run state
This test is used to check that the EEP added to the received packet in the previous test was actually added. The test also checks that no FCT's are output until the state changes to Run, i.e:-
- Data is not input by the FIFO via the Input Data Interface, but then is input during Run state.
- Data is output by the FIFO via the Output Data Interface (EEP should be seen).
- FCT's are not output by the FIFO via the Output FCT Interface, but then are output during Run state.
The test is set-up such that:-
- Data is not provided to the FIFO.
- Data can be taken from the FIFO at the maximum data rate..
- FCT's can be taken from the FIFO at the maximum data rate.
The Data In handshake signal should show no handshakes throughout the test, but the Data Out handshake signal should show frequent handshakes until the FIFO becomes empty. The FCT handshake signal should show only seven handshakes during the Run state and none during the Error Reset state.
Test 12 (110us to 1s) - Total Chaos!
This test is used to try and break the FIFO design by operating it in totally random states, with input Data that has random gaps between the transfers, output Data that has random gaps between the transfers and also FCT's that have random gaps between the transfers. Initially the FIFO is filled to 50% but after that everything is random and chaotic, i.e:-
- Data is input by the FIFO via the Input Data Interface.
- Data is output by the FIFO via the Output Data Interface.
- FCT's are output by the FIFO via the Output FCT Interface.
The test is set-up such that:-
- Data is provided to the FIFO with a 0 to 1 cycle gap between transfers.
- Data can be taken from the FIFO but has a 0 to 10 cycle gap between transfers.
- FCT's can be taken from the FIFO but have a 0 to 7 cycle gap between transfers.
The three handshake signals should show frequent handshakes taking place throughout the test. No data should be lost and no lone EEP should be seen coming out of the FIFO. The Output Data interface should output packets terminated with EEP's, which are in effect disconnected packets.
If any of the three handshake signals stop before the full 50 million NChar's go though the FIFO (1 second of simulation time) then the FIFO is behaving incorrectly. Likewise if the self-checking testbench reports an error to the simulator window then the FIFO is also behaving incorrectly.
Note that this test produces many illegal states and also state transitions that would never occur during normal CODEC operation.
