Part 2 - Create & build 1st firmware project
Missing Image!Missing Image!Missing Image!

Introduction

This tutorial details the steps required for using Vivado to create a very simple ARM Cortex-A9 based processor design for the ZedBoard hardware.

Aims

The aims of this tutorial are as follows :-
  1. Setup environment
  2. Create project area
  3. Launch Vivado
  4. Create project
  5. Create block design
  6. Add IP to block design
  7. Re-customize IP
  8. Validate block design
  9. Generate output products
  10. Create HDL wrapper
  11. Generate bitsteam
  12. Export hardware platform
  13. Archive project
  14. Commit to repository

1. Setup environment

Setup Xilinx design environment for the 2020.2 toolset.
steve@Linux-Steve:/home/steve$ source xilinx.sh
Xilinx tools available tools at /opt/Xilinx :-
1) 2020.2 - Vivado - SDK - Vitis - PetaLinux
0) Exit
Please select tools required or exit : 1

Tools are as follows :-
vivado @ /opt/Xilinx/Vivado/2020.2/bin/vivado
vitis @ /opt/Xilinx/Vitis/2020.2/bin/vitis
petalinux-build @ /opt/Xilinx/PetaLinux/2020.2/tool/tools/common/petalinux/bin/petalinux-build

2. Create project area

Create the project directory along with a subdirectory for the firmware.
steve@Linux-Steve:/home/steve$ mkdir -p /home/steve/projects/hello_world/fw

3. Launch Vivado

Launch Vivado quietly from a Terminal.
steve@Linux-Steve:/home/steve$ vivado -nojournal -nolog -notrace &

4. Create project

The Vivado start window will now appear. Create a project by clicking on Create Project within the Vivado 2020.2 window. Missing Image! Review the information the in the New Project : Create a New Vivado Project window and then click Next. Missing Image! In the New Project : Project Name window set Project Name to project, Project location to /home/steve/projects/hello_world/fw & untick Create project subdirectory. Click Next to proceed. Missing Image! No additional source files are required for this project so in the New Project : Project Type window tick the Do not specify sources at this time check box and then click Next. Missing Image! Select the ZedBoard hardware in the New Project : Default Part window by clicking on the Boards tab, selecting ZedBoard Zynq Evaluation and Development Kit and then clicking Next. Missing Image! Look over the project details in the New Project : New Project Summary window and then click Finish. Missing Image! The Vivado project window now appears.

5. Create block design

Create a block design by clicking on Create Block Design under the IP INTEGRATOR heading inside the Flow Navigator section. Missing Image! Tip: The buttons in the top menu bar of a pane provide a very useful way of expanding the working area of that pane. Maximize Missing Image! expands a pane within the project window. Float Missing Image! expands the pane beyond the project window. Restore Missing Image! reverses Maximise. Dock Missing Image! reverses Float.

The Create Block Design dialog now appears. Change the Design name to system and then click OK Missing Image! The Vivado project window now changes to reflect the addition of the Diagram pane. Expand the Diagram pane outside of the Vivado window by clicking on its Float icon Missing Image!. Missing Image!

6. Add IP to block design

Add IP to the block design by clicking on the Missing Image! button. Missing Image! Scroll down to the ZYNQ7 Processing System in the pop-up dialog and add this to the block design by double clicking on it. Missing Image! The ZYNQ7 Processing System IP is now added to the block design. Let Vivado automate some of the connections by clicking on Run Block Automation. Missing Image! Review the connections proposed in the Run Block Automation dialog and then click OK. Missing Image! Some of the connections are now made in the block design.

7. Re-customize IP

Begin re-customization of the ZYNQ7 Processing System by double clicking on it. Missing Image! The Re-customize IP window now appears. Missing Image! The M_AXI_GP0_ACLK connection on the ZYNQ7 Processing System is not required for this design and will cause an error if left unconnected. Remove this by clicking on PS-PL Configuration, expanding AXI Non Secure Enablement, expanding GP Master AXI interface and then unticking M AXI GP0 interface. Missing Image! Remove the USB connection from the ZYNQ7 Processing System as it is not required for this design. Click on MIO Configuration, expand I/O Peripherals and untick USB 0. Missing Image! Remove the Timer connection from the ZYNQ7 Processing System as it is not required for this design. Click on MIO Configuration, expand Application Processor Unit and untick Timer 0. Missing Image! The FCLK_CLK0 connection on the ZYNQ7 Processing System is not required for this design. Remove this by clicking on Clock Configuration, expanding PL Fabric Clocks and then unticking FCLK_CLK0. Missing Image! Commit the changes made to the ZYNQ7 Processing System by clicking on OK.

8. Validate block design

Verify the block design is error free by clicking on the Validate Design icon Missing Image! in the Diagram pane or by pressing F6. Missing Image! The above should result in the following dialog being presented, click OK to dismiss this. If errors are found in the block design review these and replay the relevant steps from above. Missing Image! Return the floating Diagram pane back to the Vivado project window by clicking on its Dock icon Missing Image!.

Save the block design by selecting Save Block Design from the File menu or by pressing Ctrl+S.

9. Generate output products

Generate the HDL files that are required for implementation, simulation and synthesis by right clicking on system.bd and selecting Generate Output Products... from the menu. system.bd can be found under the expanded Design Sources inside the Sources tab of the BLOCK DESIGN section. Missing Image! The Generate Output Products dialog now appears. Select the required options (defaults as shown are fine) and then click Generate. Missing Image!

10. Create HDL wrapper

Create a top-level wrapper for the block design since block designs cannot be the top-level of a design. Right click on system.bd and select Create HDL Wrapper... from the menu. Missing Image! The Create HDL Wrapper dialog now appears. Select Let Vivado manage wrapper and auto-update and then click OK. Missing Image! Float the Sources pane and fully expand the Design Sources to see the full design hierarchy which now includes the HDL wrapper. Dock the Sources pane after viewing. Missing Image!

11. Generate bitsteam

Generate the programmable logic bitstream by clicking on Generate Bitstream under the PROGRAM AND DEBUG heading inside the Flow Navigator section.

The No Implementation Results Available dialog will appear on the very first run of any new project. Proceed by clicking Yes. Since synthesis and implementation have not yet been run these will be scheduled to run before the bitstream generation. Missing Image! The Launch Runs dialog now appears. Select the required options (defaults as shown are fine) and then click OK. Missing Image! Once the bitstream generation is complete the Bitstream Generation Completed dialog will appear. Click Cancel to dismiss this. Missing Image! The generated bitstream can now be found in the impl_1 directory.
steve@Linux-Steve:/home/steve$ ls -la /home/steve/projects/hello_world/fw/project.runs/impl_1/*.bit
-rw-rw-r-- 1 steve steve 4045674 Feb  4 17:06 /home/steve/projects/hello_world/fw/project.runs/impl_1/system_wrapper.bit

12. Export hardware platform

Export the hardware platform by selecting File » Export » Export Hardware... from Vivado's top menu.

The Export Hardware Platform dialog now appears. Review the information provided and click Next. Missing Image! The Export Hardware Platform : Output dialog now appears. Include the generated bitstream in the exported hardware by selecting include bitstream and then clicking Next. Missing Image! The Export Hardware Platform : Files dialog now appears. Export the hardware to the Vitis project directory by changing the Export to location to /home/steve/projects/hello_world/fw and then clicking Next. Missing Image! The Export Hardware Platform : Exporting Hardware Platform dialog now appears. Review the information provided and then click Finish. Missing Image! The exported hardware platform is a single zip file with a .xsa extension instead of a .zip. The contents of this file can be viewed by using the zip utility.
steve@Linux-Steve:/home/steve$ unzip -l /home/steve/projects/hello_world/fw/system_wrapper.xsa
Archive:  /home/steve/projects/hello_world/fw/system_wrapper.xsa
E4//KOlLgGdrrL0lLA+eMRgk6crcc+UH5B/jIndhUWBKI=
  Length      Date    Time    Name
---------  ---------- -----   ----
     2296  2021-02-04 17:11   xsa.json
     1178  2021-02-04 17:11   xsa.xml
  2735810  2021-02-04 17:11   ps7_init.html
     2235  2021-02-04 17:11   system.bda
  4045674  2021-02-04 17:11   system_wrapper.bit
   515497  2021-02-04 17:11   ps7_init.c
    69596  2021-02-04 17:11   zed_board.jpg
    33562  2021-02-04 17:11   ps7_init.tcl
     3675  2021-02-04 17:11   ps7_init.h
     1201  2021-02-04 17:11   sysdef.xml
     4279  2021-02-04 17:11   ps7_init_gpl.h
    76171  2021-02-04 17:11   system.hwh
   516101  2021-02-04 17:11   ps7_init_gpl.c
---------                     -------
  8007275                     13 files

13. Archive project

Create a Tcl script so the project can be regenerated and revision controlled (optional). Select File » Project » Write Tcl... from the main menu. In the Write Project to Tcl dialog set Output File to /home/steve/projects/hello_world/fw/project.tcl & tick Recreate Block Designs using Tcl. Click OK to proceed. Missing Image! Click Yes in the Write Project to Tcl dialog to view the created Tcl file. Missing Image! Review project.tcl paying particular attention to any files listed below the following section in the header. There are no additional files listed for this project.
  1. # NOTE: In order to use this script for source control purposes, please make sure that the
  2. #       following files are added to the source control system:-
To prevent the tcl script from creating a project directory the directory name must be removed from the create_project command.
steve@Linux-Steve:/home/steve$ cd /home/steve/projects/hello_world/fw
steve@Linux-Steve:/home/steve/projects/hello_world/fw$ sed -i 's/create_project ${_xil_proj_name_} .\/${_xil_proj_name_}/create_project ${_xil_proj_name_}/g' project.tcl

14. Commit to repository

To commit the minimum set of files into repository the following steps are required :-
  1. Create a SVN repository in the repos area.
  2. Checkout the empty repository into the project area.
  3. Add the fw directory to the change list.
  4. Add the project.tcl file to the change list.
  5. Commit the changes along with a comment.
steve@Linux-Steve:/home/steve/projects/hello_world/fw$ cd ..
steve@Linux-Steve:/home/steve/projects/hello_world$ svnadmin create /home/steve/repos/hello_world
steve@Linux-Steve:/home/steve/projects/hello_world$ svn checkout file:///home/steve/repos/hello_world .
steve@Linux-Steve:/home/steve/projects/hello_world$ svn add -N fw
steve@Linux-Steve:/home/steve/projects/hello_world$ svn add fw/project.tcl
steve@Linux-Steve:/home/steve/projects/hello_world$ svn commit -m "Basic Zedboard design consisting of just the ZYNQ7 Processing System"

'projects' location : 'repos' location : 'downloads' location :
Copyright © 2021 Steve Haywood
Missing Image!
Missing Image!Missing Image!Missing Image!