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SpaceWire Switch Core Testbench
The VHDL SpaceWire testbench provides a complete test harness around the SpaceWire Switch Core (Router) and allows data to be generated, examined and consumed.

The testbench philosophy is based on the above three requirements:-
  • A need to generate input data.
  • A need to consume output data.
  • A need to examine data flow.
Separating these requirements into modules yields:-
  • PGive generates SpaceWire data under the control of an external file.
  • PTake consumes SpaceWire data under the control of an external file.
  • PSnoop examines and reports SpaceWire data flow to an external file.
An illustration of how these modules are connected together to form a Switch Core testbench is given below:-


The testbench top-level can be used to test any configuration of the Switch Core having anywhere between 2 and 32 ports.

Listed below are some example stimuli that can be used to test a 4 port version of the Switch Core (1 user port plus 3 external ports).



Example 1 - Nice & Easy
This example shows a fixed packet flow from a single input port to a single output port using hardware addressing.

PGive Stimulus PTake Stimulus PSnoop Generated Reports
Inputs Outputs
give_01.txt take_01.txt input_01.txt output_01.txt
give_02.txt take_02.txt input_02.txt output_02.txt
give_03.txt take_03.txt input_03.txt output_03.txt

The two important reports to examine in this example are input_02.txt and output_03.txt. The following point should also be noted from this example:-
  • The header byte (first byte) is deleted from all hardware addressed packets by the switch.



Example 2 - Bottleneck
This example shows a fixed packet flow from every input port to a single output port using hardware addressing.

PGive Stimulus PTake Stimulus PSnoop Generated Reports
Inputs Outputs
give_01.txt take_01.txt input_01.txt output_01.txt
give_02.txt take_02.txt input_02.txt output_02.txt
give_03.txt take_03.txt input_03.txt output_03.txt

The four important reports to examine in this example are input_01.txt, input_02.txt, input_03.txt and output_02.txt. The following point should also be noted from this example:-
  • The input packets appear on the output port in an evenly distributed (round-robin) fashion.



Example 3 - Everything to Everywhere
This example shows random packet flow from every input port to every output port using hardware addressing.

PGive Stimulus PTake Stimulus PSnoop Generated Reports
Inputs Outputs
give_01.txt take_01.txt input_01.txt output_01.txt
give_02.txt take_02.txt input_02.txt output_02.txt
give_03.txt take_03.txt input_03.txt output_03.txt

All reports are worth examining in this example and for readability the first byte of each packet is set to the number of the input port where it originated.



Example 4 - User Port
This example shows how to communicate with the internal User Port.
  • User Port packets start with a header of 0 and are followed by the command bytes.
PGive Stimulus PTake Stimulus PSnoop Generated Reports
Inputs Outputs
give_01.txt take_01.txt input_01.txt output_01.txt
give_02.txt take_02.txt input_02.txt output_02.txt
give_03.txt take_03.txt input_03.txt output_03.txt

The two important reports to examine in this example are input_01.txt and output_01.txt. The following point should also be noted from this example:-
  • The User Port automatically returns command responses to the port that requested them.



Example 5 - Logical Addressing
This example shows how to set-up and use two Logical Addresses, one with header deletion and one without.
  • Logical Address 60 shall represent Hardware Address 3 and will delete headers from its packets.
  • Logical Address 75 shall represent Hardware Address 2 and will not delete headers from its packets.
PGive Stimulus PTake Stimulus PSnoop Generated Reports
Inputs Outputs
give_01.txt take_01.txt input_01.txt output_01.txt
give_02.txt take_02.txt input_02.txt output_02.txt
give_03.txt take_03.txt input_03.txt output_03.txt

The three important reports to examine in this example are input_01.txt, output_02.txt and output_03.txt. The following points should also be noted from this example:-
  • Packets addressed to Logical Address 60 come out on port 3 with their headers deleted.
  • Packets addressed to Logical Address 75 come out on port 2 with their headers remaining.



Example 6 - Grouping
This example shows how to set-up and use two Grouped Logical Addresses, one with header deletion and one without.
  • Logical Address 32 shall represent Hardware Address 1 or 2 and will delete headers from its packets.
  • Logical Address 33 shall represent Hardware Address 2 or 3 and will not delete headers from its packets.
PGive Stimulus PTake Stimulus PSnoop Generated Reports
Inputs Outputs
give_01.txt take_01.txt input_01.txt output_01.txt
give_02.txt take_02.txt input_02.txt output_02.txt
give_03.txt take_03.txt input_03.txt output_03.txt

All reports are worth examining in this example and for readability the first byte of each packet is set to the number of the input port where it originated. The following points should also be noted from this example:-
  • Packets addressed to Logical Address 32 come out on ports 1 or 2 with their headers deleted.
  • Packets addressed to Logical Address 33 come out on ports 2 or 3 with their headers remaining.
  • The first few Logical Addressed packets get swallowed by the switch because they arrive before the Logical Addresses are set-up.



Example 7 - Disconnected Ports
This example shows how Grouped Logical Addressed packets are automatically routed to the available and connected ports. For this example to work the active signal assignment in the testbench module must be commented out and the process beneath it uncommented.
  • Logical Address 50 shall represent Hardware Address 1, 2 or 3 and will remove headers from its packets.
PGive Stimulus PTake Stimulus PSnoop Generated Reports
Inputs Outputs
give_01.txt take_01.txt input_01.txt output_01.txt
give_02.txt take_02.txt input_02.txt output_02.txt
give_03.txt take_03.txt input_03.txt output_03.txt

All reports are worth examining in this example and for readability the first byte of each packet is set to the number of the input port where it originated. The following points should also be noted from this example:-
  • When all ports are active packets go to ports 1, 2 or 3.
  • When port 1 becomes disconnected (at 1us) packets go to ports 2 or 3.
  • When ports 1 and 3 become disconnected (at 3us) packets go to port 2 only.



Summary
The above stimuli only touch the surface of what is possible with PGive, PTake and PSnoop. By using the full capabilities of these modules comprehensive testbenches can be created within a very short space of time.