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Raptor-16 Interrupt Mechanism
The Raptor-16 Microprocessor has seven prioritized interrupts that operate using the very simple request/acknowledge mechanism shown below.

Instigating an interrupt is achieved by setting its Request input high and leaving it in this state until its Acknowledge output is pulsed. The Acknowledge output will only be pulsed after the interrupt code has been fully executed and the processor is currently executing the RTI (Return From Interrupt) instruction.

Unless an interrupt is required to be repeated then once its Acknowledge output is pulsed its Request input should immediately be set low.

When the processor detects an interrupt request it executes it immediately if it is not currently executing an higher priority request. If an higher priority request is currently being executed then the lower priority request will be held pending until the higher priority request is completed.

All interrupts can be interrupted by higher priority interrupts, except for interrupt 7, which has the highest priority.

An interrupt is started by a request and then followed by the processor executing the following internally generated code:-

Move CR,-(SP) ; Save Control Register on Stack.
Move PC,-(SP) ; Save Program Counter on Stack.
Move #IntNo,CR ; Set Interrupt Level to Interrupt Number.
MoveQ #IntNo,PC ; Execute Interrupt Code.

An interrupt is ended by the execution of a RTI instruction, which is actually the execution of the following internally generated code:-

Move (SP)+,PC ; Restore Program Counter from Stack.
Move (SP)+,CR ; Restore Control Register from Stack.

Please do not worry about the internally generated code, this is only given to show what order things are pushed and popped on and off the stack. The only point to remember here is that interrupts cannot interrupt the execution of the internally generated code, this is required to safeguard the correct entrance and exit to and from an interrupt.

By default the processor will not detect any interrupt requests, since the Interrupt Mask in the Control Register will be set to "0000000". To enable interrupts the appropriate bits in the Interrupt Mask must be set.

If interrupts are not required then the processor can be used to execute code from the very first memory location (address 0). However when interrupts are enabled, memory locations 1 through 7 MUST contain interrupt code, which will usually be either a BraQ or a RTI instruction. With Interrupts enabled memory location 0 MUST contain an instruction that causes program execution to continue after the interrupt code.

An example section of code that uses 3 out of the 7 interrupts to control an incremental word sequence on Port 0 can be found here.

The most important thing to bare in mind when using interrupts in the stack. Since Raptor-16 does not have a separate System Stack then the User Stack (SP) must be set-up in advance with enough free space for the both the user code and also the interrupt code.

Each interrupt saves at the very least 2 words of data on the stack and with all 7 interrupts enabled there is the possibility of nesting, which would require 14 words of free stack space plus the extra spaces for subroutine jumps and register pushes contained in both the user and interrupt code.